1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor and a metal contact for a semiconductor device.
2. Description of the Related Art
As the integration density of a semiconductor device increases, the pitch size and margins for an etching process decrease. Thus, for example, in a case where a deep and small metal contact (DSMC) process is performed to selectively pattern a dielectric layer having a step difference of 20,000 xc3x85 or greater to form a metal contact, numerous problems may occur during the photolithography and etching processes. The DSMC process is mainly applied to a capacitor with a bit line structure or a multi-layered interconnection structure, and thus it is important to effectively solve those processing problems.
In most cases, the above described metal contact is formed using two metal contact step sequences. Specifically, in a first sequence of steps, a first dielectric layer is formed on a bit line. When the step difference or thickness of the first dielectric layer reaches about 10,000 xc3x85, a process for forming a first metal contact is carried out. The process for forming the first metal contact comprises the steps of forming a first contact hole through the first dielectric layer and thereafter depositing a first metal layer in the first contact hole, thereby forming a metal plug or a metal stud. The metal may be comprised of tungsten, or other metal with similar properties.
Next, in a second sequence of steps, a process for forming a second metal contact comprises the steps of forming a second dielectric layer on the first dielectric layer and the metal plug or the metal stud, forming a second contact hole through the second dielectric layer to expose the metal plug or the metal stud, and then depositing a second metal layer in the second contact hole and on the second dielectric layer, thereby forming a metal interconnection layer connected to the metal plug or the metal stud. A process for forming a capacitor is additionally performed between the two processes of forming first and second metal contacts.
However, these processes for forming a metal contact and a capacitor are very complicated and may cause productivity to decrease, especially if not properly performed. In addition, since the process for forming a first metal contact is performed before the process for manufacturing a capacitor, metal contact resistance may increase due to the influence of the subsequent processes. In other words, the contact resistance of the metal plug or the metal stud, formed by the process for forming a first metal contact, may increase due to heat budgets that accompany a subsequent process for forming a silicon nitride layer or a heat treatment process for forming a capacitor.
FIG. 11 illustrates the increase in contact resistance due to the heat budget. As shown in FIG. 11, as the heat budgets that accompany the subsequent processes increase, the contact resistance of a metal contact, such as the metal stud or metal plug, increases. In particular, when a heat budget of a temperature of 750xc2x0 C. or greater is present, the contact resistance goes up dramatically. The increase in the contact resistance of a metal contact may have a negative influence and thereby degrade the high-speed operations of a semiconductor device.
To solve the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device including a metal contact and a capacitor, which is capable of preventing the increase in the contact resistance of a metal contact due to heat budget, and in addition, simplifies the whole manufacturing process by overcoming a high step difference between dielectric layers.
Accordingly, to achieve the above object, there is provided a method of manufacturing a semiconductor device. First, gate structures are formed on a semiconductor substrate, and a first dielectric layer is formed on the semiconductor substrate to cover the gate structures. A bit line is then formed on the first dielectric layer and a second dielectric layer is formed on the first dielectric layer to cover the bit line. A buried contact is formed to be electrically connected to the semiconductor substrate between the gate structures by etching the second dielectric and first dielectric layer. A third dielectric layer is then formed on the second dielectric layer. A lower electrode of a capacitor, a dielectric layer, and an upper electrode are formed to be connected to the buried contact. A fourth dielectric layer is formed to cover the capacitor. A plurality of contact holes are formed to expose the upper electrode, the bit line, an active region of the semiconductor substrate, and the gate structures by selectively etching the fourth dielectric layer and the underlying dielectric layers. A plurality of metal contacts are formed to be electrically connected to the upper electrode, the semiconductor substrate, the bit line, and the gate structures by filling the contact holes.
The plurality of contact holes may be formed after the first through fourth dielectric layers have been deposited, or preferably, in two steps, by first forming lower contact hole regions before forming the third dielectric layer, and then forming upper contact hole regions that are aligned with and communicate with the lower contact hole regions.
The lower contact hole regions are formed by selectively etching the second dielectric layer and first dielectric layer to expose the bit line, the conductive pattern of one of the gate structures, and the semiconductor substrate. Then, the third dielectric layer is formed of a material having discrete step coverage characteristics which cause voids to form within the plurality of lower contact hole regions while depositing the third dielectric layer over the second dielectric layer.
In other words, the third dielectric layer has inferior step coverage (i.e., poor fluidity), when it is deposited over the second dielectric layer, which thereby seals the opening each of the plurality of lower contact hole regions and precludes additional material of the third dielectric layer from forming in the lower contact hole regions.
In addition, an etching stopper may be further formed between the third dielectric layer and the second dielectric layer.
An ohmic layer may be further formed under the plurality of metal contacts to be in ohmic-contact with the plurality of metal contacts, and may be formed to cover the sides and the bottoms of the plurality of lower contact holes after the plurality of lower contact holes are formed. Alternatively, the ohmic layer may be formed on the upper and lower hole regions after the upper hole regions are formed.
According to the present invention, it is possible to omit the step of forming a metal plug or a metal stud, thereby simplifying the whole manufacturing process. In addition, it is possible to prevent damage to the active region of a semiconductor substrate or an upper electrode caused by over-etching in the case of simultaneously forming a variety of metal contact holes.